3D ICs utilizing through Silicon Via are the latest tendency in the market. TSV can be used for 3D stacking at different integrating degrees: from via first ( front terminal procedure ) to via last ( back terminal procedure ) . The electrical public presentation of the device, refill stuffs and cost are affected by the type of via integrating that is chosen. The paper discusses the Deep Reactive Ion Etching ( DRIE ) procedure as applied to plan vias of different sizes, forms and deepness. Using the DRIE technique, really high facet ratios may be achieved in the via first attack as the breadth of the via is limited. In via last attack nevertheless, via is wider which in bend reduces the aspect ration but allows for higher etch rates.
The Through-hole Si via ( TSV ) has been accepted as the feasible solution to organize 3D ICs and emerged as a critical technique to guarantee continued grading, miniaturisation, higher denseness for high public presentation devices. The advantage of TSV is that, integrating of both homogenous and heterogenous french friess are possible in a individual bundle. The 3D IC industry is traveling from the R & A ; D phase to the commercialisation phase and therefore the economic costs will keep a greater sway on the engineering being adopted for mass production. TVS, typically requires some extra procedure stairss which are as follow. ( one ) Dry etching of vias or holes utilizing DRIE. ( two ) Dielectric isolation bed deposition. ( three ) Via make fulling utilizing Cu electroplating, followed by CMP. ( four ) Wafer thinning and adhering. Use of via first, via last or via center is mostly application dependant. Though via last and via center are largely in usage today, attempts are in advancement to gravitate to the via first procedure from a cost-efficient point of position. Several techniques are available for via hole boring like optical maser boring, DRIE and photolithography. Amongst these, the DRIE is the most widely used technique to accomplish high facet ratio. This paper discusses the usage of DRIE to organize each of the different via integrating
Deep RIE is a procedure that is used to accomplish etch deepness of 100s of micrometers with about perpendicular sidewalls. Two techniques may be used for high rate DRIE: cryogenic and Bosch procedure. However, merely the Bosch procedure is used for production. In Bosch procedure, two different gas composings are alternated in the chamber. Plasma incorporating sulfur hexafluoride ( SF6 ) ions is used to accomplish a faster anisotropic etch, while octaflurocyclobutane ( C4F8 ) is used to lodge the chemically inert passivation bed. C4F8 creates the polymer on the surface of the substrate, while SF6 etches the surface. During the physical etching, the polymer is sputtered off on the horizontal surface, go forthing the sidewalls integral. Since the polymer dissolves easy, it builds up and protects the sidewalls during chemical portion of etching. Hence this procedure provides for really high facet ratio of about 50 to 1. The etch and sedimentation stairss are repeated to organize a big figure of really little isotropic stairss at the underside of the engraved cavities. Cycle clip may be adjusted optimally. Short rhythms give drum sander walls while longer 1s provide higher etch rates.
Fig. 1. Profile of a DRIE trench with overdone scallop consequence.
VIA FIRST BEFORE BEOL
The via first integrating procedure is used to organize the TSV in wafer fab during the front terminal procedure. The via formed utilizing this method are normally little in size with characteristic size runing from 2-5 um diameter to 30-50 um deepness [ 1 ] . These high facet ratio vias are used for higher denseness interconnects.
Fig. 2. Via first earlier FEOL
From left to compensate: DRIE, Oxidation, Poly-silicon replenishment
After the via formation, the wafer will undergo further treating stairss. The replenishing stuff has to be such that, it can defy temperatures greater than 1000 grades. Hence by and large poly-silicon is used for this intent. The advantage of poly-silicon procedure is that it does non necessitate any seed bed and the isolation bed may be deposited utilizing the conventional oxidization procedures. On the other manus, poly-silicon replenishment procedure is possible merely for via breadths lower than 5 um. To accomplish etch deepnesss of around 150 um or high facet ratio of 30, we need to utilize the DRIE with a modified Bosch procedure. Besides, taper, joust, and the sidewall raggedness have to be tightly controlled to guarantee the subsequent procedures are non affected. For optimal consequences, fluidic ion and impersonal denseness are believed to be of import. An advanced plasma beginning based on ICP, to supply a combined solution on RF yoke, gas injection, magnetic parturiency, stuffs, geometry etc. is used in with a P type Electrostatic chow to supply angle divergences less than 0.2 grades.
Fig. 3. Angle divergence across a 200 nanometer wafer
For the procedure to be quotable, the camber has to be clean, so that there is no physique up of procedure stuffs along the chamber walls and etch procedure taint is avoided. The advantage of via first before FEOL is that merely a individual DRIE equipment demand to be added to the procedure flow and therefore itaa‚¬a„?s a cost effectual integrating.
VIA FIRST AFTER BEOL
The vias fabricated utilizing this method are typically larger with sizes runing from 10-40 um diameter to 70-120 um deepnesss. These vias besides used to be referred to as via center.
Fig. 4. Via foremost after BEOL
From left to compensate: DRIE, Oxidation, Cu replenishing
The greatest advantage of this procedure is that vias are formed after the CMOS processing stairss, which means a replenishing stuff like Cu ( as opposed to poly-silicon ) , with better electrical and thermic belongingss may be used, without the concern of exposure of wafer to high temperature processes. Fabrication demands are similar to via first before FEOL nevertheless, the dielectric beds that were a portion of the FEOL procedure have to be removed utilizing normally used dielectric etch procedures.
Fig. 5. Via foremost after BEOL after DRIE and after replenishing
After the replenishing measure has been carried out, a barrier bed and seed bed have to be deposited utilizing PVD and CVD, which is an expensive and clip devouring procedure. Normally a taper of 83 to 85 grades is required to supply a good measure coverage for metal. An alternate method that has been developed to run into the above demands while besides being fast and cheap is, the aa‚¬A“open oral cavity processaa‚¬A? . This procedure involves making a characteristic that enlarges the via entryway hole. This proposed procedure uses the SF6 and C4F8 mixture ab initio to make a 70 grade taper for a deepness of about 30 um. Then Bosch procedure is applied for anisotropic etch to obtain a taper angle of 88.8 grades up to a deepness of 180 um.
Fig. 6. Top: Ideal profile ; Bottom: unfastened oral cavity profile
An mean etch rate of around 12 um/min may be obtained with uniformities of +/- 2.5 % utilizing this combined procedure as shown in fig. 7.
Fig. 7. 60umX180um via hole
Since the wafer will be subjected to further cutting, the etch deepness is usually limited to 100 um. As the facet ratio in such instances will be low ( 5 to 10 ) , a high etch rate may be obtained.
High etch rate
To accomplish high etch rates and a high selectivity for exposure resist, high dissociation utilizing high plasma denseness and low plasma potency for high selectivity are needed. Standard RIE systems are non good suited for this intent as they inherently have a high DC prejudice which in bend agencies low selectivity. The Inductively Coupled Plasma ( within High Density Plasma beginnings ) is an appropriate pick as it can bring forth HDP ( 1011 to 1012 ions/cm-3 ) , provide high gas dissociation and low potency at really high force per unit areas. The F groups move to the Si surface within gas stage and react with it to bring forth volatile SiF4 which are so pumped out from the system.
Si ( s ) + 4F ( g ) AA SiF4 ( g ) + G0 ( eq 1 )
Parameters like flow rate, force per unit area and ICP power may be set to obtain a specific partial force per unit area ( F ) needed to take Silicon. The Si etch rate is known to be straight relative to the figure of fluorine groups making the surface.
Fig. 8 Fluorine extremist flux rate Vs Si etch rate
Very high etch rates of 50 um/min may be obtained by this method. But as etch rate additions, effectual control to obtain an unvarying etch throughout the wafer decreases. Hence a P type Electrostatic chow is used to give a unvarying temperature distribution of +/- 0.15 grade over the wafer.
IV.VIA LAST AFTER BEOL
In the integrating schemes described antecedently, vias are etched blind up to a certain specified deepness from the device side. However, in the via last attack, since, vias are created after the bonding and cutting, they have to be etched from the rear of the wafer. The dimension of the via is larger than that formed by the via last technique being 5-50um diameter and 30-150 um deepness. The vias are etched to a halt bed, normally the first dielectric bed of the FEOL device.
Fig. 9. Via last after BEOL
From left to compensate: DRIE, Oxidation, Cu replenishing
During the operation, the device wafer is temporarily bonded to the wafer bearer, which is normally glass. This wafer adhering restricts further stairss to a temperature of 180 to 200 grades.
DRIE for high facet ratio oxide etch
A major issue in via last attack is that the rear via metallization should be in contact with the metal tablet. To get the better of this, the insulating oxide bed should be dry etched to the metal tablet after DRIE. After this a con formal dielectric bed should be deposited at low
temperature and the dielectric bed
should be cleared from the bottom via so that the barrier may be deposited and the seed bed may be in contact with the metal tablet. The dielectric etch measure can be carried out without much trouble if the via profile is about perpendicular. If the profile is tapered, photolithography measure demands to be to boot carried out to take the dielectric bed from the underside of via but at the same clip maintaining a midst sidewall to supply good electrical isolation. This demand for a really specific lithography for a really high facet via is a major restriction for the credence of the via last attack. However, the available engineering, i.e. , HDP dielectric etcher, used to take insulating beds beneath metal tablets may be extended to be applicable for high facet ratio etching of the inhumed oxide bed after DRIE of Si as shown in Fig. 10.
Fig. 10. Etching profile of inhumed oxide bed below Si bed.
The inhumed Oxide bed was removed at an etch rate of 500 um/min, with a 10:1 selectivity as compared to the exposure resist mask used to specify the characteristic.
Different integrating strategies like Via foremost ( anterior to FEOL ) , Via foremost ( after BEOL ) and Via last ( after BEOL ) were examined and the challenges in the etching procedures of each of these vias were addressed. The available engineering was further drawn-out and applied to buried oxide bed etch. The bing Bosch procedure was applied with minor alterations as suited to each via integrating procedure demand, to either facilitate greater aspect ratio, or higher etch rate as required.