Now battery technology is increasing battery size

Now a days the Personal computing
devices and wireless communication systems demand high speed computation with
low power consumption123. There are many reasons for
demanding low power consumption. Main reason is to increase the battery life
time of portable devices. Another drawback in battery technology is increasing battery size due to
higher energy capacity. The second reason is the reliability of the system. If
the power dissipation is more then we should provide heat sink or cooling
device. Otherwise electrical parameter shift will occur. Indirectly packaging
cost of the device is also increasing. So to overcome all these issues, design
a device which will consume less power. To do a high speed computations an
efficient arithmetic logic unit is needed. Full adder is an important block in
ALU. So in this paper, we propose a 1-bit & 8-bit Full adder which will
consume low power using PTL logic

Various Logic styles have been proposed
for designing Full Adder. Static CMOS full adder with pull up and pull down
transistor has been proposed which provide full swing output. But speed of the
system is degraded due to high input capacitance.4 In the same paper complementary pass transistor logic style  has been proposed which is having full swing
output, high speed and high power dissipation.5 Full
adder is designed with transmission function which is having low power
dissipation but low driving capability.6} A new full adder
is proposed based on multiplexer which impacts with threshold problem on its
output node.3 Formal Design Procedure is developed using K-map and
Pass network theorem for designing Full adder with 6 transistor of XOR-XNOR
cell which doesn’t have threshold voltage problem. But  some more design effort is needed for sizing
of the device.4

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I.     Proposed Method

Pass Transistor
Logic is used in integrated Circuits to reduce the number of transistors in the
circuit by eliminating redundant transistor. It uses fewer transistor so it
will have more speed and low power consumption. So in the proposed work full
adder is designed with pass transistor Logic

A.    Logic Equations:

The Full adder will
have 2 inputs A, B one carry in C and 2 outputs Sum and Carry out. The Logic
equation of full adder is as follows:

SUM= AB

Carry out  = AB+BC+CA

                   = AB+BC(A+A’)+CA(B+B’)

                   = AB+ABC+A’BC+AB’C

                   =AB(1+C)+(AB’+A’B)C

                   =AB+( AB)C

B.   
Proposed
Circuit

               

The basic module of full adder circuit is XOR and XNOR gate. By using
simple OR, NOT and AND gate, we can design 
these modules. The main factor we have to consider is number of transistors
used. If it increases then it will affect the power dissipation and delay.
Considering all these factors, circuit has been designed. The First transistor
M1 is generating the output AB’ while M3 is generating output A’B. The two
outputs together generate (AB) at point P. Outputs of M2 and M4 are
A’B’ and AB respectively. They produce AB at point Q. The logic at the outputs
of M5 and M6 are (AB)C’ and (AB)C. They are generating the
sum output in the following manner

Sum = (AB)C’+( AB)’C = ABC

Similarly the output logic of M7
and M8 are generated carry value. The proposed full adder circuit is shown
below.

 

 

Figure 1: Proposed full adder

 Table 1
will explain the logic values at the output levels  of transistor for different input combinations
of the circuit.

A

B

C

M1

M2

M3

M4

M5

M6

M7

M8

SUM

CARRY

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

0

1

0

0

1

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

1

1

0

0

1

0

0

0

0

1

0

1

1

0

0

1

0

0

0

1

0

0

0

1

0

1

0

1

1

0

0

0

0

0

0

1

0

1

1

1

0

0

0

0

1

0

0

1

0

0

1

1

1

1

0

0

0

1

0

1

1

0

1

1

 

Table 1: Truth table for proposed full adder

                For
8-bit full adder, ripple carry adder is used. Ripple carry adder is created
using cascading multiple adders. Each full adder input carry in is a carry out
of previous adder.              In 8-bit full adder, to add
two bytes of data together, adder looking after the rightmost column of binary
digits would indeed need to be nothing more than a half adder.    However all the adders to the left of that
need to able to accept three inputs- two digit from their column and any carry
from next column to the right. Figure 2 explains the circuit connection for
8-bit full adder. Here 8 numbers of 1-bit full adder are connected in cascade
form to make 1-bit full adder into 8-bit full adder.

 

 

    

Figure
2: 8-bit Full Adder

Truth table will
give the  logical output for all possible
output. The truth table for 8-bit full adder using ripple carry adder is given
as follows:

A

B

Cin

Cout

F

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

 

Table
2: Truth table for ripple carry adder

                                                                                                                                           
II.    Simulation Results

                All the
simulations are performed on microwind 3.5 and DSCH 3.5 using 65nm. Microwind
is an electronic automation tool for designing integrated circuits in physical
level. Before designing the circuit, architecture is validate at the logic
level using DSCH module in Microwind. DSCH module is used to evaluate the power
consumption.

The main concept of the work is to face
all challenges  in designing 1-bit and
8-bit full adder circuit using NMOS method based on Pass transistor logic. This
work develops a NMOS design methodology for full adder circuit combining gates
of different logic to same circuit in an effort to obtain improved performance
compared to XOR method.

               

                Layout design
explains the placement of components in integrated circuit during fabrications.
The Layout of 1-bit full adder using NMOS is given below:

Figure 3: Layout diagram of 1-bit
full adder

               

The simulation diagram is very important to verify their logic.
From the simulation diagram, we can check the function of the circuit. In
figure 4 the truth table of full adder is verified.The simulation results of
1-bit full adder using NMOS is given below

 

Figure 4: Simulation diagram of
1-bit full adder

 

 

                In figure 5,
the Layout of 8-bit full adder using NMOS is described. It will give the
placement of components and routing i.e interconnection to the components.

               

Figure 5: Layout diagram of 8-bit
full adder

 

                In figure 6
the truth table is verified with truth table. Here Eeach input carrys 8-bit.The
simulation results of 8-bit full adder using NMOS is given below

 

Figure 6: Simulation diagram of 8-bit
full adder

Power consumption can be calculated  using DSCH module in Microwind Software. In
figure 7 power consumption of the proposed method is calculated.

 

          

 

Figure 7: Simulation diagram of 1-bit
full adder

 

The given below table will describe the comparison between
proposed 1-bit full adder method and XOR method in terms of area, power and
frequency. In our proposed methods the number of transistors are reduced.
Because of that area also get reduced. Our main aim of reducing power
consumption also achieved. In all theses parameters we had a better results in
our proposed method only.

 

No.of Transistors

Area(µm)

Power(mw)

XOR

16

9X8

7.03

Proposed method
(1-bit full adder)

8

8X8

5.913

Table 3: Comparison of full adder
designs

The Table 4 will give the comparison between 1-bit full adder and
8-bit full adder in terms of number of transistors used power consumption. Here
in 8-bit full adder, the number of transistors and power consumption are
increased. But when we are comparing with XOR method, this output is
reasonable.

 

Parameter

No. of Transistor

Power (mW)

1 bit Full Adder

8

5.913

8 bit Full Adder

64

9.25

 

Table 4: Comparison of 1-bit and
8-bit full adder

                                                                                                                                                      
III.   Conclusion

                The layout
simulation results of the proposed method is compared with previous reported
circuits and result analysis shows that proposed full adder circuits consumes
less power and area as compared to other full adder circuits. The performance
degradation at higher load capacitance is a major concern of this proposed
method and needs to be eliminated in future with the help of other advanced
technologies.

 

 References

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Karimi, Abdalhoosein Rezai, Mohammed Mahdi                                           
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5     
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6     
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7     
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8     
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9     
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10  
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